Flash memories have become increasingly popular in recent years. A typical flash memory comprises a memory array having a large number of flash memory cells arranged in blocks. One of the most commonly known flash memories is the one-transistor flash memory, wherein each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding charges and is separated from source and drain regions contained in a substrate by a layer of thin oxide (tunneling oxide). Each of the memory cells can be electrically charged by injecting electrons from the drain region through the tunneling oxide layer onto the floating gate. The charges can be removed from the floating gate by tunneling the electrons to the substrate through the tunneling oxide layer during an erase operation. Thus, the data in a memory cell is determined by the presence or absence of charges in the floating gate.
In current state-of-the-art non-volatile memories, high voltage (typically ranging from 9V to 20V) is typically used in cell operations (e.g., erase and program operations) in order to achieve desired memory states. Infrastructure for on-chip high voltage generation is thus essential to support the memory cell operations and has become an essential block in non-volatile memories and products. The infrastructure involves separate sets of transistors used for handling high voltages and typically adds at least five extra masks to a conventional CMOS technology. Therefore, it complicates the process technology for non-volatile memories.
Another issue on the high voltage infrastructure is its scalability along new generation technology. The high voltage is found un-scalable or difficult to be scaled due to the physics employed in memory cell operation. In contrast, the operating voltage for logic circuits has been continuously scaled down during the past decades along with the scaling of the minimum geometry of CMOS technology. An increasingly larger gap between voltages operating the logic circuits and the memory cells is observed. The issue is more pronounced and aggravated as CMOS technology is scaled beyond 0.25 μm generation. As a result, a larger overhead, in terms of the area occupied by the high voltage circuitry, is often seen in newer generation memory products (in both stand-alone and embedded non-volatile memory products). The scaling limits for high voltage circuitry further imposes constraints on the scaling of the minimum feature size for high-voltage transistors. Often, the same sets of design rules for high-voltage transistors are used from one generation of products to the next. Furthermore, the high voltage operation introduces more issues in product functionality and reliability area.
U.S. Pat. No. 6,958,513 discusses a flash memory cell capable of operating under low operation voltages, which may be, for example, as low as about 5 volts. The structure of the flash memory cell is illustrated in FIG. 1, which includes a floating gate 2 formed in a well region 4, a control gate 6 over floating gate 2, and a top poly gate 8 over control gate 6. The top poly gate 8 and control gate 6 are separated by a first insulator 10, and control gate 6 and floating gate 2 are separated by a second insulator 12. In a program operation, a negative bias is applied to top poly gate 8 with respect to control gate 6, and thus electrons are injected into control gate 6 from top poly gate 8. The second insulator 12 has a conduction band level lower than the energy level of the electrons, and thus the electrons are ballistic-injected into floating gate 2, which acts as the storage layer of the flash memory cell. In an erase operation, a positive bias is applied to top poly gate 8 with respect to control gate 6, and thus the holes are injected into control gate 6 from top poly gate 8. Second insulator 12 has a valence band lower than the energy level of the holes, and thus the holes are ballistic-injected into floating gate 2. The operation voltages of the above-discussed flash memory cell are far lower than other commonly used flash memory cells. However, to achieve ballistic tunneling through second insulator 12, the voltage applied between control gate 6 and top poly 8 is preferably high in order to increase the energy levels of electrons and holes to surmount the respective conduction band and valence band.
Ideally, the operation voltages of flash memory cells are desired to be the same as operation voltages of core integrated circuits. Although this is still a hard-to-reach target currently, it is preferable to lower operation voltages of flash memory cells as much as possible. New methods for further lowering operation voltages are thus needed.